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AT86RF232
7.1.3 Interrupt Handling
All interrupts provided by the Atmel AT86RF232 (see Table 6-10 ) are supported in
Basic Operating Mode.
For example, interrupts are provided to observe the status of radio transceiver RX and
TX operations.
On reception IRQ_2 (RX_START) indicates the detection of a valid PHR first,
IRQ_5 (AMI) an address match and IRQ_3 (TRX_END) the completion of the frame
reception.
On transmission IRQ_3 (TRX_END) indicates the completion of the frame transmission.
Figure 7-2 shows an example for a transmit/receive transaction between two devices
and the related interrupt events in Basic Operating Mode. Device 1 transmits a frame
containing a MAC header (in this example of length seven), payload and valid FCS. The
frame is received by Device 2 which generates the interrupts during the processing of
the incoming frame. The received frame is stored in the Frame Buffer.
The first interrupt IRQ_2 (RX_START) signals the reception of a valid PHR.
If the received frame passes the address filter, refer to Section 7.2.3.4 , an address
match interrupt IRQ_5 (AMI) is issued after the reception of the MAC header (MHR).
In Basic Operating Mode the third interrupt IRQ_3 (TRX_END) is issued at the end of
the received frame. In Extended Operating Mode, refer to Section 7.2 ; the interrupt is
only issued if the received frame passes the address filter and the FCS is valid. Further
exceptions are explained in Section 7.2 .
Processing delay t IRQ is a typical value, refer to Section 12.4 .
Figure 7-2. Timing of RX_START, AMI and TRX_END Interrupts in Basic Operating Mode.
TRX_STATE
-16 0
PLL_ON
128
160
192
BUSY_TX
192+(9+ m )*32
PLL_ON
Time [μs]
SLP_TR
IRQ
Typ. Processing Delay
t TR10
IRQ_3 (TRX_END)
Number of Octets
Frame Content
4
Preamble
1
SFD
1
PHR
7
MHR
m
MSDU
2
FCS
TRX_STATE
IRQ
Interrupt latency
RX_ON
IRQ_2 (RX_START)
t IRQ
BUSY_RX
IRQ_5 (AMI)
t IRQ
RX_ON
TRX_END
t IRQ
35
8321A – MCU Wireless – 10/11
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